This application claims the benefit of a Japanese Patent Application No. 2002-177990 filed Jun. 19, 2002, in the Japanese Patent Office, the disclosure of which is hereby incorporated by reference.
1. Field of the Invention
The present invention generally relates to electronic circuit design methods, simulation apparatuses and computer-readable storage media, and more particularly to an electronic circuit design method which is suited for automatically carrying out a high-speed wiring process, a simulation apparatus which uses such an electronic circuit designing method, and a computer-readable storage medium which stores a program for causing a computer to design an electronic circuit using such an electronic circuit design method.
2. Description of the Related Art
When designing electronic circuits such as a large scale integrated (LSI) circuits, multi chip modules (MCMs) and printed circuit boards (PCBs) by computer aided design (CAD), a noise analysis is carried out by simulation and noise countermeasures are taken with respect to the noise depending on the results of the noise analysis. The noise analyzed by the noise analysis includes reflection noise and crosstalk noise. The reflection noise is generated due to mismatch of characteristic impedances of a transmission line and an internal resistance of a driver. On the other hand, the crosstalk noise greatly depends on a driving capability of the driver and a gape (pitch) of adjacent wiring patterns.
The noise countermeasures refer to various measures which are taken to suppress various kinds of noise generated in the electronic circuit, based on the results of the noise analysis. Recently, due to the small size and high operation speed of electronic circuits, the noise analysis and the noise countermeasures have become very important when designing the electronic circuit.
The design of the electronic circuit is modified, if necessary, based on the noise countermeasures which are determined. After this design modification, a noise analysis is carried out again, and the procedure described above is repeated until the noise falls within a tolerable range.
According to the conventional electronic circuit design method, if the noise analysis is carried out and a wiring pair where the generated noise exceeds the tolerable range is detected, for example, a designer makes a design modification such as increasing a spacing between the wirings of the wiring pair to correct the wirings, and the noise analysis is carried out again. If the generated noise still exceeds the tolerable range when the noise analysis is carried out again, it is necessary to make a further design modification such as further correcting the wirings. When making the design modification, the designer must specify the modifying contents in detail. However, when the wiring traffic is heavy, it may not be possible to secure all of the specified spacings, and in such a case, the designer specifies the wirings for which the spacings are to be secured based on the designer's experience.
Accordingly, when the generation of the noise exceeding the tolerable range is detected by the noise analysis, the designer must repeat the design modification and the noise analysis a plurality of times, and there was a problem in that it takes time to design the electronic circuit. In addition, the required number of design modifications tends to increase when the designer is inexperienced, and there was another problem in that the dependency on the designer and the load on the designer are both high.